The present invention relates to a semiconductor integrated circuit device having a dynamic RAM (DRAM) cell and, more particularly, to prevent the data retention characteristics of the memory cells from deteriorating due to capacitive coupling between the word and bit lines.
Of MOS semiconductor memory devices, DRAMs are integrated at the highest density because memory cells forming the DRAM are relatively simple. This trend toward higher integration is due partly to increasing miniaturization. However, as device dimensions shrink, capacitive coupling between signal lines and therefore interference noise between signal lines increase. Reduction in interference noise is one key for realizing a high-density, high-speed DRAM.
The present inventors have found interference noise arising from capacitive coupling between the word and bit lines to be one type of interference noise between signal lines. This will be explained in detail.
FIG. 11 is an equivalent circuit diagram showing the memory cell array of a DRAM. FIG. 11 shows a memory cell array of the folded bit-line scheme. The folded bit-line scheme is the major stream of current DRAMs.
As shown in FIG. 11, in the folded bit-line scheme, memory cells M are arranged not at all the intersections of word lines WL (WL0 to WL7) and bit lines BL (bBL0, BL0, bBL1, BL1, and bBL2) but at half of all the intersections. In general, the contact (to be referred to as a bit line contact hereinafter) of a switching transistor ST of the memory cell M with respect to the bit line BL is shared by adjacent memory cells M.
In the folded bit-line scheme, two types of coupling capacitors, i.e., a coupling capacitor CWB1 at an intersection where a memory cell M is located, and a coupling capacitor CWB2 at an intersection where no memory cell M is located exist as coupling capacitors between the word lines WL and bit lines BL. The capacitances of the coupling capacitors CWB1 and CWB2 are different from each other.
As the design geometries shrink further, and the word line pitch comes closer to the minimum processing size, a self-aligned contact technique is required for the bit line contact. FIG. 12 shows a bit line contact using the self-aligned contact technique.
FIG. 12 is a sectional view showing the memory cell array taken along a bit line. Note that a trench capacitor memory cell is exemplified as the memory cell M.
As shown in FIG. 12, according to the self-aligned technique, the gate electrode (word line WL) of the switching transistor ST of the memory cell M is covered with a silicon nitride (SiN) film 121. A bit line contact 122 is formed in self-alignment with the gate electrode using the silicon nitride film 121 as an insulating film for insulating the gate electrode from the bit line BL. In the self-aligned contact technique, the gate electrode is formed from a conductive film 123 functioning as a word line WL and an insulating (SiO.sub.2) film 124 formed on the conductive film 123. The top of the gate electrode is insulated from the bit line BL by the insulating film 124.
Using this self-aligned contact technique eliminates the alignment margin between the bit line contact and gate electrode and contributes to reduction in cell size. However, the word line WL has a relatively high dielectric constant and is insulated from the bit line BL by the thin silicon nitride film 121. This greatly increases the coupling capacitor at the bit line contact 122, i.e., the coupling capacitor CWB1.
At an intersection where no memory cell M is located, the bit line contact need not be formed, and only a thick silicon oxide (SiO.sub.2) film 125 exists between the word line WL and bit line BL. Therefore, the capacitance of the coupling capacitor CWB2 is smaller than the capacitance of the coupling capacitor CWB1.
As represented by the self-aligned contact technique, the advance of miniaturization along with an increase in integration degree disturbs balance between the coupling capacitors CWB1 and CWB2 more and more. The unbalance between the coupling capacitors CWB1 and CWB2 generates interference noise on an inactive word line. This will be explained with reference to FIG. 13.
FIG. 13 is a circuit diagram showing the arrangement of a conventional DRAM.
FIG. 13 schematically shows a memory cell array 131 of the folded bit-line scheme including bit lines, memory cells M, and word lines, sense amplifiers S/A for sensing and amplifying a signal from the memory cell M, and word line driving circuits WDRV for activating a specific word line WL (WL0 to WL7) in order to select a memory cell M.
The sense amplifiers S/A are divided into a right sense amplifier group "S/A-RIGHT" and a left sense amplifier group "S/A-LEFT". The groups "S/A-RIGHT" AND "S/A-LEFT" sandwich the memory cell array 131 and extend parallel to the word lines WL.
The word line driving circuits WDRV are divided into an upper word line driving circuit group "WDRV-UPPER" and a lower group "WDRV-LOWER". The groups "WDRV-UPPER" and "WDRV-LOWER" sandwich the memory cell array 131 and extend parallel to the bit lines BL.
Bit lines BL0, bBL0, BL2, and bBL2 are respectively connected to the sense amplifiers S/A belonging to the group "S/A-RIGHT", whereas bit lines BL1, bBL1, BL3, and bBL3 are respectively connected to the sense amplifiers S/A belonging to the group "S/A-LEFT".
Word lines WL0, WL1, WL4, and WL5 are respectively connected to the driving circuits WDRV belonging to the group "WDRV-UPPER", whereas word lines WL2, WL3, WL6, and WL7 are respectively connected to the driving circuits WDRV belonging to the group "WDRV-LOWER".
The sense amplifiers S/A and driving circuits WDRV are divided in order to relax the layout pitch of the circuit.
FIG. 14 is a timing chart showing operation of the DRAM shown in FIG. 13. FIG. 15 is a circuit diagram showing the state of the memory cell array in sensing. FIG. 16 is a circuit diagram showing the state of the memory cell array in precharging.
As shown in FIG. 14, the DRAM is activated when a row address strobe signal bRAS changes from "H" level to "L" level. After the DRAM becomes active, an address is received from outside the DRAM, and a specific word line (word line WL2 in FIG. 14) is activated in accordance with the received address.
Assume that the word line WL2 is activated to "H" level, as shown in FIG. 15. At this time, all the word lines WL0, WL1, and WL3 to WL7 except for the word line WL2 are inactive at the ground potential.
Further, assume that data "1" are read out from all the memory cells M connected to the word line WL2.
In this case, a small potential is read out as memory data of the memory cell M onto the bit lines BL0 to BL3 and slightly increases the potentials of the bit lines BL0 to BL3. Subsequently, the sense amplifiers S/A are activated to sense and amplify the increased potentials. As a result, the bit lines BL0 to BL3 are charged to a high potential (e.g., power supply potential), and the bit lines bBL0 to bBL3 are discharged to a low potential (e.g., ground potential). The inactive word lines WL0, WL1, WL4, and WL5 are capacitively coupled with the bit lines bBL0 to bBL3, the inactive word lines WL3, WL6, and WL7 are capacitively coupled with the bit lines BL0 to BL3, and interference noise is generated on these inactive word lines WL0, WL1, and WL3 to WL7.
If the capacitance of the coupling capacitor CWB1 is equal to the capacitance of the coupling capacitor CWB2, complementary interference noise components are generated on the inactive word lines WL0, WL1, and WL3 to WL7. Apparently, no interference noise is generated on the inactive word lines WL0, WL1, and WL3 to WL7.
However, the capacitance of the coupling capacitor CWB1 is larger than the capacitance of the coupling capacitor CWB2. The inactive word lines WL3, WL6, and WL7 capacitively couple with the bit lines BL0 to BL3 more strongly. The inactive word lines WL0, WL1, WL4, and WL5 capacitively couple with the bit lines bBL0 to bBL3 more strongly.
As shown in FIG. 15, so-called positive interference noise the potential of which rises from the ground potential is generated on the inactive word lines WL3, WL6, and WL7. So-called negative interference noise the potential of which drops from the ground potential is generated on the inactive word lines WL0, WL1, WL4, and WL5.
FIG. 17 is a circuit diagram showing an example of the word line driving circuit WDRV.
As shown in FIG. 17, the driving circuit WDRV comprises a noise killer transistor Q1. The noise killer transistor Q1 applies the ground potential to the corresponding word line when it is inactive. Interference noise generated on the inactive word line is finally absorbed by a ground power supply line VSS via the noise killer transistor Q1.
The resistance of the word line WL is not completely "0". Therefore, if interference noise is generated on an inactive word line, the potential of the inactive word line continuously varies for the time determined by the time constants of this word line and the line path connecting the word line WL to the ground power supply line VSS.
Particularly positive interference noise raises the potential of the inactive word line WL. This increases any leakage current flowing through the source and drain of the switching transistor ST. Consequently, charges (memory data) leak from the memory cell M to degrade the data retention characteristics.
As shown in FIG. 15, positive interference noise is maximized when data "1" are read out from all the cells or when data "0" are read out from all the cells. This is the worst case, but this worst case becomes more prominent in the layout of the word line driving circuits shown in FIGS. 13 and 15.
In the layout shown in FIGS. 13 and 15, the driving circuits WDRV belonging to the group "WDRV-LOWER" drive the word lines WL2, WL3, WL6, and WL7, and the driving circuits WDRV belonging to the group "WDRV-UPPER" drive the word lines WL0, WL1, WL4, and WL5.
The word lines WL2, WL3, WL6, and WL7 are strongly capacitively coupled with the bit lines BL0 to BL3 via the coupling capacitors CWB1, whereas the word lines WL0, WL1, WL4, and WL5 are strongly capacitively coupled with the bit lines bBL0 to bBL3 pairing with the bit lines BL0 to BL3 via the coupling capacitors CWB1.
In this layout, for example, when data "1" are read out from all the cells, as shown in FIG. 15, all negative interference noise is transmitted to the group "WDRV-UPPER", and all positive interference noise is transmitted to the group "WDRV-LOWER".
The ground power supply line VSS is divided into local ground power supply lines "VSS-UPPER" and "VSS-LOWER". The local ground power supply line "VSS-UPPER" is shared by the driving circuits WDRV of the group "WDRV-UPPER", and the local ground power supply line "VSS-LOWER" is shared by the driving circuits WDRV of the group "WDRV-LOWER". These local ground power supply lines "VSS-UPPER" and "VSS-LOWER" respectively have given finite ground power supply line resistances "RVSS". Hence, interference noise generated on an inactive word line generates AC power supply noise on the local ground power supply lines "VSS-UPPER" and "VSS-LOWER" until the interference noise is absorbed by the "trunk" ground power supply line "VSS-LINE".
In the layout shown in FIGS. 13 and 15, all negative or positive interference noise is transmitted to the local ground power supply lines "VSS-UPPER" and "VSS-LOWER". Accordingly, the AC power supply noise is very large.
For example, when all positive interference noise is transmitted to the local ground power supply line "VSS-LOWER", the potential of the local ground power supply line "VSS-LOWER" greatly varies in the positive direction (positive power supply noise), as shown in FIG. 14. While the local ground power supply line "VSS-LOWER" varies, the potentials of the inactive word lines WL3, WL6, and WL7 connected to the local ground power supply line "VSS-LOWER" vary in the positive direction. This considerably degrades the data retention characteristics of the memory cells M.
As shown in FIG. 15, all negative interference noise is transmitted to the local ground power supply line "VSS-UPPER". As a result, as shown in FIG. 14, the potential of the local ground power supply line "VSS-LOWER" greatly varies in the negative direction. Note that negative potential variations do not directly degrade the data retention characteristics.
When the row address strobe signal bRAS changes from "L" level to "H" level to precharge the DRAM, the potential of the bit line BL charged or discharged to the power supply potential or ground potential is equalized to the precharge potential. During precharging, the same interference noise as that in sensing is generated. This is shown in FIG. 16.
As shown in FIG. 16, positive interference noise generated on the word lines WL0, WL1, WL4, and WL5 in precharging generates positive power supply noise on the local ground power supply line "VSS-UPPER". Accordingly, the data retention characteristics of the memory cells M connected to the word lines WL0, WL1, WL4, and WL5 degrade considerably.
As described above, in a very-large-scale DRAM in which fine elements are integrated, either positive interference noise or negative interference noise is generated locally on one inactive word line due to capacitive coupling between the word and bit lines. The local interference noise generates large power supply noise on the ground power supply line until it is completely absorbed by the ground power supply line. Such large power supply noise considerably degrades the data retention characteristics of the memory cell.